The present invention relates to a semiconductor device, and more particularly to a technique suitable for use in a semiconductor device into which, for example, a semiconductor wafer is diced.
In a manufacturing process of the semiconductor device, a plurality of semiconductor devices are formed over the semiconductor wafer. Thereafter, the semiconductor wafer is diced to separate the individual semiconductor devices as semiconductor chips. In this situation, a crack may be generated in an end (scribe line region) of each semiconductor chip by dicing, and spread into a circuit region within the semiconductor chip. As a technique for preventing the spread of the crack, a seal ring (or a guard ring) is known in the prior art. The seal ring is formed of a metal member stacked to penetrate through a plurality of inter-layer insulating films disposed over a semiconductor substrate. The seal ring is annularly disposed to surround the circuit region.
For example, Japanese Unexamined Patent Application Publication No. 2004-304124 (US2004/0195582(A1)) discloses a semiconductor device. The semiconductor device has a circuit formation region which is a region of a circuit formed over the semiconductor substrate. The semiconductor device includes a first guard ring, a second guard ring, and a first connection portion. In order to prevent moisture from entering the circuit formation region from a periphery thereof, the first guard ring surrounds the periphery of the circuit formation region. The second guard ring is disposed between the circuit formation region and the first guard ring, and surrounds the periphery of the circuit formation region. The first connection portion connects the first guard ring and the second guard ring, and divides a region between the first guard ring and the second guard ring into a plurality of sections. In this technique, in order to prevent the entry of moisture, the seal ring that surrounds the circuit formation region is as least doubled, and the respective seal rings are connected to each other. With this configuration, moisture is prevented from entering the circuit formation region, and a crack generated at the time of dicing is prevented from spreading into the circuit formation region.
Also, Japanese Unexamined Patent Application Publication No. 2004-153015 (US2004/0084777(A1)) discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first insulating film, a second insulating film, a wiring structure, a first dummy pattern, and a second dummy pattern. The first insulating film is formed over the semiconductor substrate. The second insulating film is formed over the first insulating film. The wiring structure is embedded in the first insulating film and the second insulating film. The first dummy pattern is formed of a first conductive layer embedded in at least a surface side of the first insulating film in the vicinity of the wiring structure. The second dummy pattern is formed of a second conductive layer embedded in the second insulating film in the vicinity of the wiring structure, and connected to the first dummy pattern through a via hole portion. In this technique, an interlayer insulating film disposed in the vicinity of the wiring structure (guard ring) is reinforced by the dummy patterns to prevent a crack or separation from being generated on an interface or in an interior of the interlayer insulating film.